Layout of memory cells

ABSTRACT

A semiconductor structure includes a first strap cell, a first read port, and a first VSS terminal. The first strap cell has a first strap cell VSS region. The first read port has a first read port VSS region, a first read port read bit line region, and a first read port poly region. The first VSS terminal is configured to electrically couple the first strap cell VSS region and the first read port VSS region.

FIELD

The present disclosure is related to layout of memory cells.

BACKGROUND

Layouts of circuit elements in integrated circuits can greatly affectperformance and die areas of the circuits. For example, a non-optimizedlayout can result in a circuit having additional circuitry and/oradditional loads to other circuits. The additional circuitry increasesthe die area of the total circuits. In some situations, the additionalloads degrade the read speed of a memory macro.

BRIEF DESCRIPTION OF THE DRAWINGS

The details of one or more embodiments of the disclosure are set forthin the accompanying drawings and the description below. Other featuresand advantages will be apparent from the description, drawings, andclaims.

FIG. 1 is a diagram of a memory macro, in accordance with someembodiments.

FIG. 2 is a diagram of a memory cell, in accordance with someembodiments.

FIG. 3 is a diagram representing a read port of a memory cell, inaccordance with some embodiments.

FIG. 4A is a diagram of two read ports connected in the columndirection, using a shared terminal, in accordance with some embodiments.

FIG. 4B is a diagram of two read ports connected in the columndirection, using a different shared terminal, in accordance with someembodiments.

FIG. 4C is a diagram of a strap cell, in accordance with someembodiments.

FIG. 4D is a diagram of a strap cell and a read port connected in thecolumn direction, in accordance with some embodiments.

FIG. 5 is a diagram of a column of read ports and strap cells, inaccordance with some embodiments.

FIG. 6 is a diagram of two columns of read ports and strap cells, inaccordance with some embodiments.

FIG. 7 is a flow chart of a method illustrating how a column is formed,in accordance with some embodiments.

FIG. 8 is a flow chart of a method illustrating how two columns areconnected, in accordance with some embodiments.

Like reference symbols in the various drawings indicate like elements.

DETAILED DESCRIPTION

Embodiments, or examples, illustrated in the drawings are disclosedbelow using specific language. It will nevertheless be understood thatthe embodiments and examples are not intended to be limiting. Anyalterations and modifications in the disclosed embodiments, and anyfurther applications of the principles disclosed in this document arecontemplated as would normally occur to one of ordinary skill in thepertinent art.

Some embodiments have one or a combination of the following featuresand/or advantages. The reference voltage (VSS) region of a strap celland the VSS region of a bit cell in a column of a memory macro share thesame first VSS contact terminal. The VSS region of a read port in anupper segment and the VSS region of a second read port in a lowersegment share the same second VSS contact terminal. As a result, wellstrap cells between the upper segment and the lower segment in thememory macro are not needed. Consequently, the die area for the memorymacro is reduced, the load for the read bit line is less, and the readspeed is improved.

Exemplary Memory Macro

FIG. 1 is a block diagram of a memory macro 100, in accordance with someembodiments.

Memory macro 100 includes a plurality of memory segments 104. Foursegments 104 are shown for illustration. A different number of memorysegments 104 is within the scope of various embodiments. Each segment104 includes two memory banks 102 sharing a row of a plurality of localinput/output circuitries (LIOs) 106. Different configurations of amemory segment 104 are within the scope of various embodiments. Eachmemory bank 102 includes a plurality of memory cells 122 (shown in FIG.2) arranged in columns and rows. A column 120 is shown for illustrationand is described in details in FIG. 5.

Address decoders 112 provide the X- or row-address of memory cells 122to be accessed for a read or a write operation of a memory cell inmemory macro 100.

Local control circuits (LCTRL) 114 control LIOs 106, including, forexample, turning on and off the read word lines and write word lines ofthe LIOs 106.

Global input/outputs (GIOs) 116 serve to transfer data between thememory cells and other circuits outside of memory macro 100.

Global control circuit (GCTRL) 110 provides the address pre-decode,clock, and other signals for memory macro 100. GCTRL 110 includes aY-decoder (not shown) that provides the Y- or column address of a memorycell.

Exemplary Memory Cell

FIG. 2 is a circuit diagram of a memory cell 122, in accordance withsome embodiments. Memory cell 122 includes two P-type metal oxidesemiconductor (PMOS) transistors P1 and P2, and six N-type metal oxidesemiconductor (NMOS) transistors N1, N2, N3, N4, N5, and N6.

The gates of NMOS transistors N3 and N4 are coupled to a write word lineWWL. A write word line WWL is coupled to the gates of transistors N3 andN4 of a plurality of memory cells 122 to a form a row of memory cells.

The gate of transistor N6 is coupled to a read word line RWL. A readword line RWL is coupled to each gate of transistors N6 of the pluralityof memory cells 122 that are coupled to a corresponding write word lineWWL.

The drain of transistor N6 is coupled to a read bit line RBL. Read bitline RBL is coupled to the drains of a plurality of transistors N6 of aplurality of memory cells 122 to form a column, such as a column 120shown in FIG. 1.

The drains of transistors N3 and N4 are coupled to a pair of write bitlines WBL and WBLB, respectively. The pair of write bit lines WBLA andWBLB is coupled to the drains of transistors N3 and N4 of the pluralityof memory cells 122 that are coupled to the corresponding read bit lineRBL.

In a write operation for a memory cell 122, write word line WWL isactivated. The logic values to be written to memory cell 122 are placedat write bit lines WBL and WBLB and are then transferred or stored atnodes ND and NDB at the sources of transistors N3 and N4, respectively.

In a read operation, read word line RWL is activated to turn ontransistor N6. Detecting the voltage value at read line RBL reveals thedata stored in nodes NDB and ND.

Transistor N5, transistor N6, a read word line RWL, and a read bit lineRBL are collectively called a read port of a memory cell 122.

Exemplary Read Port Layouts

FIG. 3 is a diagram of a layout of a read port (RPRT) 300 of a memorycell 122, in accordance with some embodiments. In terms of a layout, aread port 300 includes a first terminal TVSS, a second terminal TRBL,and a third terminal TPOLY. Terminal TVSS is formed on a source regionof transistor N5. Terminal TRBL is formed on a drain region oftransistor N6. For simplicity, the source region of transistor N5 andthe drain region of transistor N6 are not shown in FIG. 3. TerminalTPOLY is formed on the gate or the poly region POLYN6 of transistor N6.Region POLYN5 represents the gate or the poly region of transistor N5.

For illustration, length LC1 is the distance between terminal TVSS andpoly region POLYN5. Length LC2 is the distance between poly regionsPOLYN5 and POLYN6. Lengths LPOLYN5 and LPOLYN6 are the widths of polyregions POLYN5 and POLYN6, respectively. In various embodiments, each oflengths LC1, LC2, LPOLYN5 and LPOLYN6 has the same length with acorresponding length of strap cell 124, which is explained in FIG. 4C.In various embodiments, each of lengths LC1, LC2, LPOLYN5 and LPOLYN6has a different length.

In some embodiment, a terminal TVSS of a read port 300 is merged into aneighboring terminal TVSS of a strap cell or of another read port 300 inthe same column. Explained in a different way, the strap cell and theneighboring read port or two neighboring read ports in a column sharethe same terminal TVSS. For example, in a column 120, if a read port 300neighbors a strap cell 124, the terminal TVSS of the read port 300 ismerged into a terminal TVSS of the strap cell 124. But if the read port300 neighbors another read port 300, then the terminals TVSS of twoneighboring read ports 300 are merged into one terminal TVSS. TerminalsTRBL of two neighboring read ports 300 in a column are also merged. Incontrast, terminals TPOLY of a pair of two neighboring read ports 300 ina row are not merged.

In some embodiments, terminals TVSS of read ports 300 in a column areelectrically coupled together and to a node configured to receive areference voltage VSS. Terminals TPOLY of transistors N6 in a row ofmemory cells 120 are electrically coupled together and to a read wordline RWL. Terminals TRBL of read ports 300 in a column in a firstsegment are electrically coupled together and to a first read bit lineRBL. Terminal TRBL of read ports 300 in the same column in a secondsegment are electrically coupled together and to a second read bit lineRBL. In some embodiments, a metal line in a metal one layer serves as aread bit line RBL. Further, a metal one layer is a first metal layerabove an active or a diffusion layer of a semiconductor structure. Ametal two layer is above a metal one layer. A metal three layer is abovea metal two layer. A metal four layer is above a metal three layer, etc.

FIG. 4A is a diagram of a pair of read ports 400 illustrating how twomemory cells 122 are electrically coupled together in the context of tworead ports 300-1 and 300-2, in accordance with some embodiments. Namesof elements of read port 300-1 are labeled with “-1,” while names ofelements of read port 300-2 are labeled with “-2.” In FIG. 4A, each of aread port 300-1 and 300-2 corresponds to a memory cell 122 (not shown inFIG. 4A). Additionally, terminals TRBL of read ports 300-1 and 300-2 aremerged as one read bit line terminal and are labeled terminal 410.Explained in a different way, two neighboring read ports 300-1 and 300-2in a column share the same read bit line terminal 410.

FIG. 4B is a diagram of a pair of read ports 450 illustrating how twomemory cells 122 are electrically coupled together, and share the sameterminal TVSS, in accordance with some embodiments. Names of elements ofread port 300-3 are labeled with “-3,” while names of elements of readport 300-4 are labeled with “-4.” In FIG. 4B, terminals TVSS of readports 300-3 and 300-4 are merged as one terminal, and are labeledterminal 460. Explained in a different way, two neighboring read ports300-3 and 300-4 share a terminal TVSS 460.

In some embodiments, a first read port 300 shares the same TRBL terminalwith a second read port 300 in the same column and/or shares the sameTVSS terminal with a third read port 300 in the same column.

FIG. 4C is a diagram of a strap cell 124, in accordance with someembodiments. A strap cell is commonly placed at a boundary of a memoryarray to protect the memory cells 122 inside the boundary. In someembodiments, a strap cell 124 includes two transistors represented bytwo poly gate regions POLY-T1 and POLY-T2. Strap cell 124 includes threeterminals TVSS, which are labeled TVSS-S1, TVSS-S2, and TVSS-S3. Inaddition, poly region POLY-T1 includes a terminal TVSS-S4, which isformed on poly region POLY-T1. In some embodiments, terminal TVSS-S4 iselectrically coupled with other terminals TVSS in memory macro 100.

For illustration, length LS1 is the distance between terminal TVSS-S3and poly region POLY-T2. Length LS2 is the distance between poly regionsPOLY-T1 and POLY-T2. Lengths LPOLY-T1 and LPOLY-T2 are the widths ofpoly regions POLY-T1 and POLY-T2, respectively. In some embodiments,lengths LS1, LS2, LPOLY-T2, and LPOLY-T1 have the same lengths aslengths LC1, LC2, LPOLYN5, and LPOLYN6 of read port 300 in FIG. 3. Insome embodiments, lengths LS1, LS2, LPOLY-T2, and LPOLY-T1 have thedifferent lengths than lengths LC1, LC2, LPOLYN5, and LPOLYN6 of readport 300 in FIG. 3.

FIG. 4D is a diagram used to illustrate a connected strap cell and readport 475 and how a strap cell 124 and a read port 300 in a column areconnected, in accordance with some embodiments. In FIG. 4D, terminalTVSS-S3 of strap cell 124 is merged with terminal TVSS of read port 300as one terminal TVSS labeled 470. Explained differently, a strap cell124 and a read port 300 share the same TVSS terminal 470. In someembodiments, a column 120 includes two strap cells 124 at two edges ofcolumn 120. A first strap cell 124 at the first edge of the columnshares a first terminal TVSS with a first neighboring read port 300, anda second strap cell 124 at the second edge of the column shares a secondterminal TVSS with a second neighboring read port 300.

FIG. 5 is a diagram of a column 120 in FIG. 1, in accordance with someembodiments. Column 120 is shown in the context of read ports 300 ofmemory cells 122. In FIG. 5, a read port 300 represents a memory cell122. For simplicity, terminal TPOLY, poly region POLYN5, and poly regionPOLYN6 of read ports 300 are not shown. Further, a reference to a columnof memory cells 122 also refers to a column of read ports 300 and viceversa.

For illustration, column 120 includes four read ports 300 in uppersegment 104-U and four read ports 300 in lower segment 104-L.Effectively, column 120 includes two pairs of read ports 400-U1 and400-U2 in upper segment 104-U and two pairs of read ports 400-L1 and400-L2 in lower segment 104-L. A different number of pairs of read ports400, a different number of read ports, and, thus, a different number ofmemory cells 122 in each of an upper and a lower segment is within thescope of various embodiments.

Column 120 also includes an upper LIO 106-U and a lower LIO 106-L. UpperLIO 106-U includes a strap cell 124-U while lower LIO 106-L includes astrap cell 124-L.

In some embodiments, the terminal TVSS of a strap cell in column 120 ismerged with the terminal TVSS of a neighboring read port 300 in the samecolumn 120. For example, in FIG. 5, terminal TVSS of strap cell 124-U ismerged with terminal TVSS of read port 300-U1 as one terminal, and islabeled VSS contact terminal 520-1. In other words, a VSS region ofstrap cell 124-U and a VSS region of read port 300-U1 share the same VSScontact terminal 520-1. Similarly, terminal TVSS of strap cell 124-L ismerged with terminal TVSS of read port 300-L1 as one terminal and islabeled terminal 520-2. Effectively, a VSS region of strap cell 124-Land a VSS region of read port 300-L1 share the same VSS contact terminal520-2. The connection between a strap cell and a read port sharing aterminal TVSS is illustrated above with reference to FIG. 4D.Additionally, a terminal TVSS of a pair of read reports 400 is mergedwith another terminal TVSS of another pair of read ports 400. In FIG. 5,the shared TVSS terminals are labeled terminals 520-3, 520-4, and 520-5.Two pairs of read ports 400 sharing the same TVSS terminal are similarto two read ports 300 sharing the same terminal TVSS, which is explainedabove with reference to FIG. 4B.

In some embodiments, a terminal TVSS 520 is formed by metals on thecorresponding diffusion area of the corresponding sources of transistorsN5. Terminals 520-1 through 520-5 in column 120 are coupled together andto a reference voltage VSS line that is formed at a metal four layer.Electrical connections between terminals TVSS 520-1 through 520-5 on thediffusion area and the VSS line on the metal four layer are throughmetal one layer, metal two layer, metal three layer, and vias betweenthe metal layers. For example, vias are used between the diffusion areaand metal lines of the metal one layer, between metal lines of the metalone layer and of the metal two layer, between metal lines of the metaltwo layer and the metal three layer, and between metal lines of themetal three layer and metal four layer.

Each of a pair of read ports 400 includes a read bit line contactterminal 410 shared by two read bit line regions of the correspondingtwo read ports. Read bit line contact terminals 410 of the pairs of readports 400-U1 and 400-U2 in upper segment 104-U are coupled together andto a read bit line RBL-U. Read bit line contact terminals 410 of thepairs of read ports 400-L1 and 400-L2 in lower segment 104-L are coupledtogether and to a read bit line RBL-L. In some embodiments, a metal lineon the metal one layer is cut into two portions so that the firstportion serves as a first read bit line and the second portion serves asa second read bit line. For example, a first portion of a metal line onthe metal one layer serves as a read bit line RBL-U, and a secondportion of the same metal one line serves as a read bit line RBL-L. Insome embodiments, the number of read ports 300, and thus the number ofmemory cells 122, coupled to a read bit line is selected based on thevalue 2^(K) where K is an integer number. As a result, exemplary numbersof read ports 300 per read bit line include 4, 8, 16, 32, etc. Further,the number of read ports 300 per read bit line is an even number.

At the boundary of upper segment 104-U and of lower segment 104-L, theterminal TVSS of a read port 300 in the upper segment 104-U is mergedwith the TVSS terminal of a read port 300 in the lower segment 104-L.For example, in FIG. 5, terminal TVSS of read port 300-U2 is merged withterminal TVSS of read port 300-L2 as one contact terminal 520-3. Inother words, read port 300-U2 and read port 300-L2 share the same TVSSterminal 520-3.

Because the terminals TVSS of read port 300-U2 at the boundary ofsegment 104-U and of read port 300-L2 at the boundary of segment 104-Lshare the same TVSS terminal 520-3, various embodiments of thedisclosure do not need to use a strap cell between the upper segment andthe lower segment. For example, various embodiments do not need to use astrap cell between segments 104-U and 104-L that have read port 300-U2and read port 300-L2, respectively. Effectively, there is not a row ofstrap cells between an upper segment 104-U and a lower segment 104-L inmemory macro 100. Consequently, the die area of memory macro 100 isreduced. An additional strap cell would operate as an additional load tocolumn 120, and would degrade the read performance of memory cells incolumn 120 in some conditions. As a result, a column 120 without theadditional strap cell in between segments 104-U and 104-L in accordancewith various embodiments of the disclosure is advantageous.

Additionally, read ports 300 in upper segment 104-U use two shared TVSSterminals 520-1 and 520-4, and read ports 300 in lower segment 104-L usetwo shared TVSS terminals 502-2 and 520-5. Additional shared TVSSterminals 520 could be needed, if read ports 300 are arranged in a waydifferent from the arrangement in FIG. 5. For example, additional TVSSshared terminals 520 would be needed if a strap cell 124 and theneighboring read port 300 share the same terminal TRBL.

FIG. 6 is a diagram illustrating how two columns 120-1 and 120-2 areconnected, in accordance with some embodiments. For illustration, astrap cell 124-U and a read port 300-U1 of each of column 120-1 andcolumn 120-2 in upper segment 104-U are shown. Other read ports 300 inupper segment 104-U are not shown. Further, read ports 300 and strapcells 124-L of columns 120-1 and 120-2 in lower segment 104-L are notshown. Effectively, FIG. 6 shows the connection of two connected strapcells and read ports 475 shown in FIG. 4D.

Connections of other read ports 300 in upper segment 104-U, read ports300, and strap cells 124-L of columns 120-1 and 120-2 in lower segment104-L should be recognizable by persons of ordinary skill in the art inview of this disclosure.

In some embodiments, terminals TVSS-S4, as shown in FIG. 4D, of twoneighboring strap cells 124-U in columns 120-1 and 120-2 are merged asone terminal used by both read ports. For example, terminals TVSS-S4 ofstrap cells 124-U of each column 120-1 and column 120-2 are merged asone TVSS contact terminal 605. In other words, strap cells 124-U ofcolumn 120-1 and column 120-2 share the same TVSS contact terminal 605.

In some embodiments, terminals TPOLY, as shown in FIG. 4D, of twoneighboring read ports 300 in columns 120-1 and 120-2 are merged as oneterminal used by both read ports. For example, terminals TPOLY of readports 300-U1 of each column 120-1 and column 120-2 are merged as onepoly contact terminal 610. In other words, read ports 300-U1 of columns120-1 and column 120-2 share the same poly contact terminal 610.

In some embodiments, the poly contact terminal 610, by way of a firstvia from the poly region POLYN6 of read ports 300-U1 in columns 120-1and 120-2 are electrically coupled to a metal line on the metal onelayer. The metal line on the metal one layer, through a second via, iselectrically connected to a metal line on the metal two layer. The polycontact terminal 610, by way of a third via from the metal line on themetal two layer is electrically coupled to a metal line on the metalthree layer. Effectively, a metal line on the metal three layer servesas a read word line to electrically couple the gates of transistors N6of read ports 300 in a row.

Connections of other additional columns 120-1 and 120-2 should berecognizable by persons of ordinary skill in the art in view of thisdisclosure. In various embodiments, a plurality of pairs of columns102-1 and 120-2 illustratively shown in FIG. 6 are formed to form twosegments 104-U and 104-L.

Exemplary Methods

FIG. 7 is a flow chart of a method 700 illustrating steps of formingcolumn 120 in FIG. 5, in accordance with some embodiments.

In step 705, terminal TVSS of strap cell 124-U is electrically coupledto terminal TVSS of read port 300-U1 through a first shared TVSS contactterminal 520-1.

In step 710, terminal TVSS of strap cell 124-L is electrically coupledto terminal TVSS of read port 300-L1 through a second shared TVSScontact terminal 520-2.

In step 715, terminal TVSS of read port 300-U2 is electrically coupledto terminal TVSS of read port 300-L2 through a third shared TVSS contactterminal 520-3.

In step 720, terminals TVSS of two neighboring pairs of read ports 400in column 120 are electrically coupled together through correspondingshared TVSS contact terminals 520-4 and 520-5.

In step 730, TVSS contact terminals 520-1, 520-2, 520-3, 520-4, and520-5 in column 120 are electrically coupled to a reference voltage VSSline.

In step 735, two terminals TRBL of a pair of read port 400 areelectrically coupled together through a corresponding shared TRBLcontact terminal 410.

In step 740, TRBL contact terminals 410 in column 120 in segment 104-Uare electrically coupled to read bit line RBL-U.

In step 745, TRBL contact terminals 410 in column 120 in segment 104-Lare electrically coupled to read bit line RBL-L.

As a result of the steps 705 to 745, column 120 illustrated in FIG. 5 isformed.

FIG. 8 is a flow chart of a method illustrating steps of forming a pairof columns 120-1 and 120-2 in FIG. 6, in accordance with someembodiments.

In step 805, two columns 120 in FIG. 5 are formed using the method ofFIG. 7. For illustration the two columns are called 120-1 and 120-2.

In step 810, each terminal TVSS-S4 of each strap cell 124-U in column120-1 and in column 120-2 is electrically coupled together through acorresponding shared TVSS contact terminal 605 as illustrated in FIG. 6.

In step 815, each terminal TPOLY of each read port 300-U1 in column120-1 and in column 120-2 is electrically coupled together through acorresponding shared poly contact terminal, such as terminal 610illustrated in FIG. 6.

A plurality of pairs of columns 120-1 and 120-2 in FIG. 6 are formed toform two segments 104-U and 104-L.

A number of embodiments have been described. It will nevertheless beunderstood that various modifications may be made without departing fromthe spirit and scope of the disclosure. For example, the varioustransistors being shown as a particular dopant type (e.g., N-type orP-type Metal Oxide Semiconductor (NMOS or PMOS)) are for illustrationpurposes. Embodiments of the disclosure are not limited to a particulartype. Selecting different dopant types for a particular transistor iswithin the scope of various embodiments. The low or high logic level(e.g., Low or High) of the various signals used in the above descriptionis also for illustration purposes. Various embodiments are not limitedto a particular level when a signal is activated and/or deactivated.Selecting different levels is within the scope of various embodiments.

In some embodiments, a semiconductor structure comprises a first strapcell, a first read port, and a first VSS terminal. The first strap cellhas a first strap cell VSS region. The first read port has a first readport VSS region, a first read port read bit line region, and a firstread port poly region. The first VSS terminal is configured toelectrically couple the first strap cell VSS region and the first readport VSS region.

In some embodiments, a structure comprises a first segment and a secondsegment. The first segment includes a first strap cell and a pluralityof first read ports. The second segment includes a second strap cell anda plurality of second read ports. A first strap cell VSS region of thefirst strap cell and a first read port VSS region of a first read portof the plurality of first read ports are electrically coupled togetherthrough a first VSS contact terminal. A second strap cell VSS region ofthe second strap cell and a second read port VSS region of a second readport of the plurality of second read ports are electrically coupledtogether through a second VSS contact terminal. A third read port VSSregion of a third read port of the plurality of first read ports and afourth read port VSS region of a fourth read port of the plurality ofsecond read ports are electrically coupled together through a third VSScontact terminal.

In some embodiments, a first VSS contact terminal is configured tocouple a first strap cell VSS region of a first strap cell and a firstread port VSS region of a first read port. A first read bit line contactterminal is configured to couple a first read bit line region of thefirst read port to a first read bit line. A second VSS contact terminalis configured to couple a second strap cell VSS region of a second strapcell and a second read port VSS region of a second read port. A secondread bit line contact terminal is configured to couple a second read bitline region of the second read port to a second read bit line. The firstread bit line is different from the second read bit line.

The above methods show exemplary steps, but the steps are notnecessarily performed in the order shown. Steps may be added, replaced,changed order, and/or eliminated as appropriate, in accordance with thespirit and scope of disclosed embodiments.

What is claimed is:
 1. A semiconductor structure comprising: a firststrap cell having a first strap cell reference voltage (VSS) region; afirst read port having a first read port VSS region, a first read portread bit line region, and a first read port poly region; and a first VSSterminal configured to electrically couple the first strap cell VSSregion and the first read port VSS region.
 2. The semiconductorstructure of claim 1 further comprising: a second strap cell having asecond strap cell VSS region; a second read port having a second readport VSS region, a second read port read bit line region, and a secondread port poly region; and a second VSS terminal configured toelectrically couple the second strap cell VSS region and the second readport VSS region, wherein, the first VSS terminal and the second VSSterminal are electrically coupled together; the first read port belongsto a first segment of a memory macro; and the second read port belongsto a second segment of the memory macro.
 3. The semiconductor structureof claim 2 further comprising: a third read port belonging to the firstsegment; a fourth read port belonging to the second segment; and a thirdVSS contact terminal configured to couple a third read port VSS regionof the third read port and a fourth read port VSS region of the fourthread port.
 4. The semiconductor structure of claim 1, further comprisinga second read port having a second read port read bit line region; and afirst read bit line contact terminal configured to electrically couplethe first read port read bit line region and the second read port readbit line region.
 5. The semiconductor structure of claim 1, wherein thefirst read port VSS region corresponds to a source region of a firsttransistor of the first read port; the first read port read bit lineregion corresponds to a drain region of a second transistor of the firstread port; and the first read port poly region corresponds to a gateregion of the second transistor.
 6. The semiconductor structure of claim1 further comprising a second strap cell, the first strap cell belongingto a first column of a memory macro and the second strap cell belongingto a second column of the memory macro; a first strap cell poly terminalconfigured to electrically couple a first strap cell poly region of thefirst strap cell and a second strap cell poly region of the second strapcell; a second read port having a second read port poly region; and afirst read port poly terminal configured to electrically couple thefirst read port poly region of the first read port and the second readport poly region of the second read port.
 7. The semiconductor structureof claim 6, wherein the first strap cell poly terminal is electricallycoupled to the first VSS terminal.
 8. The semiconductor structure ofclaim 1, wherein the first VSS terminal is electrically coupled to a VSSline through a first via between a diffusion area and a first metallayer, a second via between the first metal layer and a second metallayer, a third via between the second metal layer and a third metallayer, and a fourth via between the third metal layer and a fourth metallayer.
 9. A structure comprising: a first segment including a firststrap cell; and a plurality of first read ports; and a second segmentincluding a second strap cell; and a plurality of second read ports,wherein a first strap cell reference voltage (VSS) region of the firststrap cell and a first read port VSS region of a first read portbelonging to the plurality of first read ports are electrically coupledtogether through a first VSS contact terminal; a second strap cell VSSregion of the second strap cell and a second read port VSS region of asecond read port belonging to the plurality of second read ports areelectrically coupled together through a second VSS contact terminal; anda third read port VSS region of a third read port belonging to theplurality of first read ports and a fourth read port VSS region of afourth read port belonging to the plurality of second read ports areelectrically coupled together through a third VSS contact terminal. 10.The structure of claim 9, wherein the first read port VSS region of thefirst read port corresponds to a source region of a first transistor ofthe first read port; the first read port further includes a first readport read bit line region and a first read port poly region; the firstread port read bit line region corresponds to a drain of a secondtransistor of the first read port; and the first read port poly regioncorresponds to a gate of the second transistor of the first read port.11. The structure of claim 9, further comprising a VSS line configuredto electrically connect the first VSS contact terminal, the second VSScontact terminal, and the third VSS contact terminal.
 12. The structureof claim 9, wherein at least one of the first VSS contact terminal, thesecond VSS contact terminal, and the third VSS contact terminal iselectrically coupled to a VSS line through a first via between adiffusion area and a first metal layer, a second via between the firstmetal layer and a second metal layer, a third via between the secondmetal layer and a third metal layer, and a fourth via between the thirdmetal layer and a fourth metal layer.
 13. The structure of claim 9,further comprising a first read bit line configured to electricallycouple a first read bit line terminal of the first read port and a thirdread bit line terminal of the third read port; a second read bit lineconfigured to electrically couple a second read bit line terminal of thesecond read port and a fourth read bit line terminal of the fourth readport.
 14. The structure of claim 9, wherein the first segment furtherincludes a third strap cell; and a plurality of third read ports; thesecond segment further includes a fourth strap cell; and a plurality offourth read ports, a third strap cell VSS region of the third strap celland a fifth read port VSS region of a fifth read port of the pluralityof third read ports are electrically coupled together through a fourthVSS contact terminal; and a fourth strap cell VSS region of the fourthstrap cell and a sixth read port VSS region of a sixth read port of theplurality of fourth read ports are electrically coupled through a fifthVSS contact terminal; and a seventh read port VSS region of a seventhread port belonging to the plurality of third read ports and an eighthread port VSS region of an eighth read port belonging to the pluralityof fourth read ports are electrically coupled together through a sixthVSS contact terminal.
 15. The structure of claim 14, further comprisinga first strap cell poly terminal configured to electrically connect afirst poly region of the first strap cell and a third poly region of thethird strap cell; a second strap cell poly terminal configured toelectrically connect a second poly region of the second strap cell and afourth poly region of the fourth strap cell; a first read port polyterminal configured to electrically connect a first read port polyregion of the first read port and a third read port poly region of thethird read port; and a second read port poly terminal configured toelectrically connect a second read port poly region of the second readport and a fourth read port poly region of the fourth read port.
 16. Thestructure of claim 14, wherein the first strap cell poly terminal andthe second strap cell poly terminal are electrically coupled togetherand to the first VSS contact terminal, the second VSS contact terminal,and the third VSS contact terminal.
 17. A method comprising: configuringa first reference voltage (VSS) contact terminal to couple a first strapcell VSS region of a first strap cell and a first read port VSS regionof a first read port; configuring a first read bit line contact terminalto couple a first read bit line region of the first read port to a firstread bit line; configuring a second VSS contact terminal to couple asecond strap cell VSS region of a second strap cell and a second readport VSS region of a second read port; and configuring a second read bitline contact terminal to couple a second read bit line region of thesecond read port to a second read bit line different from the first readbit line.
 18. The method of claim 17, wherein a third read port VSSregion of a third read port and a fourth read port VSS region of afourth read port are electrically coupled together through a third VSScontact terminal; a third read bit line region of the third read port iselectrically coupled to the first read bit line through a third read bitline contact terminal; and a fourth read bit line region of the fourthread port is electrically coupled to the second read bit line through afourth read bit line contact terminal.
 19. The method of claim 17,further comprising configuring a first poly contact terminal to couple afirst read port poly region of the first read port to a third read portpoly region of a third read port, wherein the first read port belongs toa first column of a memory macro and the third read port belongs to asecond column of the memory macro.
 20. The method of claim 17, wherein aplurality of first read ports of a first segment of a memory macro areelectrically coupled to the first read bit line; and a plurality ofsecond read ports of a second segment of the memory macro areelectrically coupled to the second read bit line.